The present invention relates to bipolar transistor logic circuits and more particularly to emitter coupled logic (ECL) circuits where pull-up delay and power consumption are reduced by using a direct-coupled pull-up scheme. Specifically, the circuit includes a PNP transistor as the pull-up device for the output node of the circuit, and the biasing of this PNP pull-up transistor is established entirely by direct tapping of the existing voltage levels in the ECL circuit, thus eliminating the need for extra biasing circuit.
The power dissipation of high-speed bipolar ECL circuits has long been known to limit their VLSI application. The power and speed limitation of the ECL circuits derives mainly from passive resistors in the delay path where the pull-up delay is limited by the collector load resistor and the pull-down delay is limited by the output emitter-follower resistor.
Recently, various active-pull-down schemes have been pursued in an effort to reduce the power consumption of the emitter-follower stage. Exemplary schemes are described, for example, in IBM Technical Disclosure Bulletin, entitled "High-Speed ECL Circuit", vol. 32, no. 4A, September 1989 pages 374-380; IBM Technical Disclosure Bulletin, entitled "High-Speed/Low-Power Charge-Buffered Active-Pull-Down ECL/NTL Circuits", vol. 33, no. 1A, June 1990, pages 470 to 472; IBM Technical Disclosure Bulletin entitled "High-Speed Low-Power ECL Circuit with an AC-Coupled Transient Current Source", vol. 33, no. 10B, March 1991, pages 31 to 33 and IBM Technical Disclosure Bulletin entitled "High-Speed, Low-Power ECL Circuit With a Darlington-Like Transient Current Source and Active-Pull-Down Driving Stage", vol. 33, no. 11, April 1991, pages 252 to 254.
These active-pull-down schemes, in general, improves the pull-down delay by replacing the emitter-follower resistor with active devices. The pull-up delay, however, is still limited by the collector load resistor and a substantial amount of power is still needed in the current switch to achieve fast switching. While an ac-coupled complementary push-pull configuration has been disclosed in U.S. Pat. No. 5,089,724 entitled "High-Speed Low-Power ECL/NTL Circuits With AC-Coupled Complementary Push-Pull Output Stage" and assigned to the same assignee as the present invention, to decouple the collector load resistor from the delay path, the approach utilizes capacitor coupling and requires careful design and extra biasing circuit for the push-and-pull transistor.